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1.8 V, 12-LVDS/24-CMOS Output, Low Power Clock Fanout Buffer ADCLK854
FEATURES
2 selectable differential inputs Selectable LVDS/CMOS outputs Up to 12 LVDS (1.2 GHz) or 24 CMOS (250 MHz) outputs <12 mW per channel (100 MHz operation) 54 fs rms integrated jitter (12 kHz to 20 MHz) 100 fs rms additive broadband jitter 2.0 ns propagation delay (LVDS) 135 ps output rise/fall (LVDS) 70 ps output-to-output skew (LVDS) Sleep mode Pin programmable control 1.8 V power supply
FUNCTIONAL BLOCK DIAGRAM
ADCLK854
VREF CLK0 CLK0 CLK1 CLK1 IN_SEL CTRL_A LVDS/ CMOS VS/2 LVDS/ CMOS OUT0 (OUT0A) OUT0 (OUT0B) OUT1 (OUT1A) OUT1 (OUT1B) OUT2 (OUT2A) OUT2 (OUT2B) OUT3 (OUT3A) OUT3 (OUT3B)
APPLICATIONS
Low jitter clock distribution Clock and data signal restoration Level translation Wireless communications Wired communications Medical and industrial imaging ATE and high performance instrumentation
CTRL_B
OUT4 (OUT4A) OUT4 (OUT4B) OUT5 (OUT5A) OUT5 (OUT5B) OUT6 (OUT6A) OUT6 (OUT6B) OUT7 (OUT7A) OUT7 (OUT7B)
GENERAL DESCRIPTION
The ADCLK854 is a 1.2 GHz/250 MHz LVDS/CMOS fanout buffer optimized for low jitter and low power operation. Possible configurations range from 12 LVDS to 24 CMOS outputs, including combinations of LVDS and CMOS outputs. Three control lines are used to determine whether fixed blocks of outputs (three banks of four) are LVDS or CMOS outputs. The ADCLK854 offers two selectable inputs and a sleep mode feature. The IN_SEL pin state determines which input is fanned out to all the outputs. The SLEEP pin enables a sleep mode to power down the device. The inputs accept various types of single-ended and differential logic levels including LVPECL, LVDS, HSTL, CML, and CMOS. Table 8 provides interface options for each type of connection. This device is available in a 48-pin LFCSP package. It is specified for operation over the standard industrial temperature range of -40C to +85C.
LVDS/ CMOS
OUT8 (OUT8A) OUT8 (OUT8B) OUT9 (OUT9A)
CTRL_C
OUT9 (OUT9B) OUT10 (OUT10A) OUT10 (OUT10B)
SLEEP OUT11 (OUT11A)
07218-001
OUT11 (OUT11B)
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
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ADCLK854 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Electrical Characteristics ............................................................. 3 Timing Characteristics ................................................................ 4 Clock Characteristics ................................................................... 5 Logic and Power Characteristics ................................................ 5 Absolute Maximum Ratings............................................................ 6 Determining Junction Temperature .......................................... 6 ESD Caution .................................................................................. 6 Thermal Performance .................................................................. 6 Pin Configuration and Function Descriptions ............................. 7 Typical Performance Characteristics ..............................................9 Functional Description .................................................................. 12 Clock Inputs ................................................................................ 12 AC-Coupled Input Applications............................................... 12 Clock Outputs ............................................................................. 12 Control and Function Pins........................................................ 13 Power Supply............................................................................... 13 Applications Information .............................................................. 14 Using the ADCLK854 Outputs for ADC Clock Applications ....................................................................................................... 14 LVDS Clock Distribution .......................................................... 14 CMOS Clock Distribution ........................................................ 14 Input Termination Options ....................................................... 15 Outline Dimensions ....................................................................... 16 Ordering Guide .......................................................................... 16
REVISION HISTORY
4/09--Revision 0: Initial Version
Rev. 0 | Page 2 of 16
ADCLK854 SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Typical (Typ) values are given for VS = 1.8 V and TA = 25C, unless otherwise noted. Minimum (Min) and maximum (Max) values are given over the full VS = 1.8 V 5% and TA = -40C to +85C variation, unless otherwise noted. Input slew rate > 1 V/ns, unless otherwise noted. Table 1. Clock Inputs and Outputs
Parameter CLOCK INPUTS Input Frequency Input Sensitivity, Differential Input Level Input Common-Mode Voltage Input Common-Mode Range Input Voltage Offset Input Sensitivity, Single-Ended Input Resistance (Differential) Input Capacitance Input Bias Current (Each Pin) LVDS CLOCK OUTPUTS Output Frequency Output Voltage Differential Delta VOD Offset Voltage Delta VOS Short-Circuit Current CMOS CLOCK OUTPUTS Output Frequency Output Voltage High Output Voltage Low Output Voltage High Output Voltage Low Reference Voltage Output Voltage Output Resistance Output Current VOH VOL VOH VOL VREF VS - 0.1 0.1 VS - 0.35 0.35 VS/2 - 0.1 VS/2 60 VS/2 + 0.1 500 250 MHz V V V V V A VCM VCMR VS/2 - 0.1 0.4 30 150 CIN -350 7 2 +350 1200 454 50 1.375 50 6 Symbol Min 0 150 1.8 VS/2 + 0.5 VS - 0.4 Typ Max 1200 Unit MHz mV p-p V p-p V V mV mV p-p k pF A MHz mV mV V mV mA Conditions Differential input Jitter performance improves with higher slew rates (greater voltage swing) Larger voltage swings can turn on the protection diodes and degrade jitter performance Inputs are self-biased; enables ac coupling Inputs dc-coupled with 200 mV p-p signal applied CLKx ac-coupled; CLKx ac bypassed to ground
Full input swing Termination = 100 ; differential (OUTx, OUTx) See Figure 9 for swing vs. frequency
VOD VOD VOS VOS ISA, ISB
247 1.125
344 1.25 3
Each pin (output shorted to GND) Single-ended; termination = open; OUTx and OUTx in phase With 10 pF load per output; see Figure 16 for swing vs. frequency @ 1 mA load @ 1 mA load @ 10 mA load @ 10 mA load 500 A
Rev. 0 | Page 3 of 16
ADCLK854
TIMING CHARACTERISTICS
Table 2. Timing Characteristics
Parameter LVDS OUTPUTS Output Rise/Fall Time Propagation Delay, Clock-to-LVDS Output Temperature Coefficient Output Skew 1 LVDS Outputs in the Same Bank All LVDS Outputs On the Same Part Across Multiple Parts Additive Time Jitter Integrated Random Jitter Symbol tR , tF tPD Min Typ 135 2.0 2.0 Max 235 2.7 Unit ps ns ps/C ps ps ps fs rms fs rms fs rms fs rms fs rms BW = 12 kHz to 20 MHz; clock = 1000 MHz BW = 50 kHz to 80 MHz; clock = 1000 MHz BW = 10Hz to 100 MHz; clock = 1000 MHz Input slew = 1 V/ns, see Figure 11 Calculated from spur energy with an interferer 10 MHz offset from the carrier 20% to 80%; CLOAD = 10 pF 10 pF load Conditions Termination = 100 differential; 3.5 mA 20% to 80% measured differentially VICM = VREF, VID = 0.5 V
1.5
50 65 390 54 74 86 150 260
Broadband Random Jitter 2 Crosstalk Induced Jitter CMOS OUTPUTS Output Rise/Fall Time Propagation Delay, Clock-to-CMOS Output Temperature Coefficient Output Skew1 CMOS Outputs in the Same Bank All CMOS Outputs On the Same Part Across Multiple Parts Additive Time Jitter Integrated Random Jitter Broadband Random Jitter2 Crosstalk Induced Jitter LVDS-TO-CMOS OUTPUT SKEW 3 LVDS Output(s) and CMOS Output(s) on the Same Part
1 2
tR, tF tPD
2.5
525 3.2 2.2
950 4.2
ps ns ps/C ps ps ps fs rms fs rms fs rms
155 175 640 56 100 260
BW = 12 kHz to 20 MHz; clock = 200 MHz Input slew = 2 V/ns, see Figure 11 Calculated from spur energy with an interferer 10 MHz offset from the carrier CMOS load = 10 pF and LVDS load = 100
0.8
1.6
ns
This is the difference between any two similar delay paths while operating at the same voltage and temperature. Calculated from the SNR of the ADC method. 3 Measured at the rising edge of the clock signal.
Rev. 0 | Page 4 of 16
ADCLK854
CLOCK CHARACTERISTICS
Table 3. Clock Output Phase Noise
Parameter CLOCK-TO-LVDS ABSOLUTE PHASE NOISE 1000 MHz Min Typ -90 -108 -117 -126 -135 -141 -146 -101 -119 -127 -138 -147 -153 -156 Max Unit dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz Conditions Input slew rate > 1 V/ns @ 10 Hz offset @ 100 Hz offset @ 1 kHz offset @ 10 kHz offset @ 100 kHz offset @ 1 MHz offset @ 10 MHz offset Input slew rate > 1 V/ns @ 10 Hz offset @ 100 Hz offset @ 1 kHz offset @ 10 kHz offset @ 100 kHz offset @ 1 MHz offset @ 10 MHz offset
CLOCK-TO-CMOS ABSOLUTE PHASE NOISE 200 MHz
LOGIC AND POWER CHARACTERISTICS
Table 4. Control Pin Characteristics
Parameter CONTROL PINS (IN_SEL, CTRL_x, SLEEP) 1 Logic 1 Voltage Logic 0 Voltage Logic 1 Current Logic 0 Current Capacitance POWER Supply Voltage Requirement LVDS Outputs LVDS @ 100 MHz LVDS @ 1200 MHz Symbol VIH VIL IIH IIL Min VS - 0.4 5 -5 8 2 VS 1.71 1.8 84 175 115 265 1.89 100 215 140 325 3 0.4 20 +5 Typ Max Unit V V A A pF V mA mA mA mA mA VS = 1.8 V 5% Full operation All outputs enabled as LVDS and loaded, RL = 100 All outputs enabled as LVDS and loaded, RL = 100 Full operation All outputs enabled as CMOS and loaded, CL = 10 pF All outputs enabled as CMOS and loaded, CL = 10 pF SLEEP pin pulled high; does not include power dissipated in the external resistors Conditions
CMOS Outputs
CMOS @ 100 MHz CMOS @ 250 MHz
SLEEP
Power Supply Rejection 2 LVDS CMOS
1 2
PSR t PD
0.9 1.2
ps/mV ps/mV
PSR t PD
These pins each have a 200 k internal pull-down resistor.
Change in tPD per change in VS.
Rev. 0 | Page 5 of 16
ADCLK854 ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Supply Voltage VS to GND Inputs CLKx and CLKx CMOS Inputs Outputs Maximum Voltage Voltage Reference Voltage (VREF) Operating Temperature Ambient Range Junction Storage Temperature Range Rating 2V -0.3 V to +2 V -0.3 V to +2 V -0.3 V to +2 V -0.3 to +2 V -40C to +85C 150C -65C to +150C
DETERMINING JUNCTION TEMPERATURE
To determine the junction temperature on the application printed circuit board (PCB), use the following equation:
TJ = TCASE + (JT x PD)
where: TJ is the junction temperature (C). TCASE is the case temperature (C) measured by the user at the top center of the package. JT is from Table 6. PD is the power dissipation. Values of JA are provided for package comparison and PCB design considerations. JA can be used for a first-order approximation of TJ by the equation
TJ = TA + (JA x PD)
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
where TA is the ambient temperature (C). Values of JB are provided in Table 6 for package comparison and PCB design considerations.
ESD CAUTION
THERMAL PERFORMANCE
Table 6.
Parameter Junction-to-Ambient Thermal Resistance Still Air 0.0 m/sec Air Flow Moving Air 1.0 m/sec Air Flow 2.5 m/sec Air Flow Junction-to-Board Thermal Resistance Moving Air 1.0 m/sec Air Flow Junction-to-Case Thermal Resistance Moving Air Die-to-Heat Sink Junction-to-Top-of-Package Characterization Parameter Still Air 0 m/sec Air Flow
1
Symbol JA
Description (Using a 2S2P Test Board) Per JEDEC JESD51-2
Value 1
Unit
42 JMA Per JEDEC JESD51-6 37 33 JB Per JEDEC JESD51-8 26 JC Per MIL-STD 883, Method 1012.1 2 JT Per JEDEC JESD51-2 0.5
C/W C/W C/W
C/W
C/W
C/W
Results are from simulations. The PCB is a JEDEC multilayer type. Thermal performance for actual applications requires careful inspection of the conditions in the application to determine if they are similar to those assumed in these calculations.
Rev. 0 | Page 6 of 16
ADCLK854 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
OUT0 (OUT0A) OUT0 (OUT0B) OUT1 (OUT1A) OUT1 (OUT1B) GND VS OUT2 (OUT2A) OUT2 (OUT2B) OUT3 (OUT3A) OUT3 (OUT3B) GND VS 48 47 46 45 44 43 42 41 40 39 38 37
VREF CLK0
1 2
PIN 1 INDICATOR
CLK0 3 GND 4 CLK1 5 CLK1 6 VS 7 OUT11 (OUT11B) 8 OUT11 (OUT11A) 9 IN_SEL 10 CTRL_A 11 CTRL_B 12
36 35 34 33 32 31 30 29 28 27 26 25
NC NC OUT4 (OUT4A) OUT4 (OUT4B) OUT5 (OUT5A) OUT5 (OUT5B) VS GND OUT6 (OUT6A) OUT6 (OUT6B) OUT7 (OUT7A) OUT7 (OUT7B)
ADCLK854
TOP VIEW (Not to Scale)
Figure 2. Pin Configuration
Table 7. Pin Function Descriptions
Pin No. 1 2 3 7, 18, 24, 30, 37, 43 5 6 8 9 10 11 12 13 14 15 16 4, 17, 23, 29, 38, 44 19 20 21 22 25 Mnemonic VREF CLK0 CLK0 VS CLK1 CLK1 OUT11 (OUT11B) OUT11 (OUT11A) IN_SEL CTRL_A CTRL_B CTRL_C SLEEP OUT10 (OUT10B) OUT10 (OUT10A) GND OUT9 (OUT9B) OUT9 (OUT9A) OUT8 (OUT8B) OUT8 (OUT8A) OUT7 (OUT7B) Description Reference Voltage. Input (Negative) 0. Input (Positive) 0. Supply Voltage. Input (Negative) 1. Input (Positive) 1. Complementary Side of Differential LVDS Output 11, or CMOS Output 11 on Channel B. True Side of Differential LVDS Output 11, or CMOS Output 11 on Channel A. Input Select. (0 = CLK0, CLK0; 1 = CLK1, CLK1). CMOS logic input with 200 k pull-down resistor. Control for Output 3 to Output 0 (0 = LVDS, 1 = CMOS). CMOS logic input with 200 k pull-down resistor. Control for Output 7 to Output 4 (0 = LVDS, 1 = CMOS). CMOS logic input with 200 k pull-down resistor. Control for Output 11 to Output 8 (0 = LVDS, 1 = CMOS). CMOS logic input with 200 k pull-down resistor. Sleep Mode Control (0 = normal operation, 1 = sleep). CMOS logic input with 200 k pull down resistor. Complementary Side of Differential LVDS Output 10, or CMOS Output 10 on Channel B. True Side of Differential LVDS Output 10, or CMOS Output 10 on Channel A. Ground Pin. Complementary Side of Differential LVDS Output 9, or CMOS Output 9 on Channel B. True Side of Differential LVDS Output 9, or CMOS Output 9 on Channel A. Complementary Side of Differential LVDS Output 8, or CMOS Output 8 on Channel B. True Side of Differential LVDS Output 8, or CMOS Output 8 on Channel A. Complementary Side of Differential LVDS Output 7, or CMOS Output 7 on Channel B.
Rev. 0 | Page 7 of 16
07218-002
NOTES: 1. NC = NO CONNECT. 2. EXPOSED PADDLE MUST BE CONNECTED TO GND.
CTRL_C SLEEP OUT10 (OUT10B) OUT10 (OUT10A) GND VS OUT9 (OUT9B) OUT9 (OUT9A) OUT8 (OUT8B) OUT8 (OUT8A) GND VS
13 14 15 16 17 18 19 20 21 22 23 24
ADCLK854
Pin No. 26 27 28 31 32 33 34 35 36 39 40 41 42 45 46 47 48 (49) Mnemonic OUT7 (OUT7A) OUT6 (OUT6B) OUT6 (OUT6A) OUT5 (OUT5B) OUT5 (OUT5A) OUT4 (OUT4B) OUT4 (OUT4A) NC NC OUT3 (OUT3B) OUT3 (OUT3A) OUT2 (OUT2B) OUT2 (OUT2A) OUT1 (OUT1B) OUT1 (OUT1A) OUT0 (OUT0B) OUT0 (OUT0A) EPAD Description True Side of Differential LVDS Output 7, or CMOS Output 7 on Channel A. Complementary Side of Differential LVDS Output 6, or CMOS Output 6 on Channel B. True Side of Differential LVDS Output 6, or CMOS Output 6 on Channel A. Complementary Side of Differential LVDS Output 5, or CMOS Output 5 on Channel B. True Side of Differential LVDS Output 5, or CMOS Output 5 on Channel A. Complementary Side of Differential LVDS Output 4, or CMOS Output 4 on Channel B. True Side of Differential LVDS Output 4, or CMOS Output 4 on Channel A. No Connect. No Connect. Complementary Side of Differential LVDS Output 3, or CMOS Output 3 on Channel B. True Side of Differential LVDS Output 3, or CMOS Output 3 on Channel A. Complementary Side of Differential LVDS Output 2, or CMOS Output 2 on Channel B. True Side of Differential LVDS Output 2, or CMOS Output 2 on Channel A. Complementary Side of Differential LVDS Output 1, or CMOS Output 1 on Channel B. True Side of Differential LVDS Output 1, or CMOS Output 1 on Channel A. Complementary Side of Differential LVDS Output 0, or CMOS Output 0 on Channel B. True Side of Differential LVDS Output 0, or CMOS Output 0 on Channel A. Exposed Paddle. The exposed paddle must be connected to GND.
Rev. 0 | Page 8 of 16
ADCLK854 TYPICAL PERFORMANCE CHARACTERISTICS
VS = +1.8 V, TA = 25C, unless otherwise noted.
2
2
07218-003
CH2 100mV
M 200ps 10.0GS/s
CH1
-36.0mV
CH2 100mV
M 1.0ns 10.0GS/s
CH1
-36.0mV
Figure 3. LVDS Output Waveform @ 1200 MHz
2.3 2.4 2.3 2.2
PROPAGATION DELAY (ns)
PROPATATION DELAY (ns)
Figure 6. LVDS Output Waveform @ 200 MHz
2.2 2.1 2.0 1.9 1.8 1.7 1.6 1.5
2.1
2.0
1.9
1.8
07218-004
0.3
0.5
0.7
0.9
1.1
1.3
1.5
1.7
400
600
800
1000
1200
1400
1600
INPUT DIFFERENTIAL (V p-p)
INPUT COMMON-MODE (mV)
Figure 4. LVDS Propagation Delay vs. Input Differential Voltage (VID)
55
DIFFERENTIAL OUTPUT SWING (mV p-p)
Figure 7. LVDS Propagation Delay vs. VICM
715
54 53 52
DUTY CYCLE (%)
705
51 50 49 48 47 46
07218-005
695
685
0
200
400
600
800
1000
1200
1.72
1.82 POWER SUPPLY (V)
1.92
FREQUENCY (MHz)
Figure 5. LVDS Output Duty Cycle vs. Frequency
Figure 8. LVDS Differential Output Swing vs. Power Supply Voltage
Rev. 0 | Page 9 of 16
07218-008
45
675 1.62
07218-007
1.7 0.1
1.4 200
07218-006
ADCLK854
900 DIFFERENTIAL OUTPUT SWING (mV p-p)
-80 -90
800
-100
PHASE NOISE (dBc/Hz)
ABSOLUTE PHASE NOISE MEASURED @ 1GHz WITH AGILENT E5052 USING WENZEL CLOCK SOURCE CONSISTING OF A WENZEL 100MHz CRYSTAL OSCILLATOR (P/N 500-06672), WENZEL 5x MULTIPLIER (P/N LNOM-100-5-13-14-F-A), AND A WENZEL 2x MULTIPLIER (P/N LNDD-500-14-14-1-D).
-110 -120 -130 -140 -150 CLOCK SOURCE -160 -170 100 1k 10k 100k 1M 10M 100M
07218-012
07218-014 07218-113
700
ADCLK854
600
500
100
200
300
400
500
600
700
800
900
1000
1100
1200
1300
1400
1500
1600
1700
400
07218-009
-180 10
INPUT FREQUENCY (MHz)
FREQUENCY OFFSET (Hz)
Figure 9. LVDS Differential Output Swing vs. Input Frequency
350 325 300 275 250
CURRENT (mA)
Figure 12. Absolute Phase Noise LVDS @ 1000 MHz
300 ALL BANKS CMOS 250 2 BANKS CMOS 1 BANK LVDS
CURRENT (mA)
225 200 175 150 125 100 75 50 25 0 200 400 600 800 1000 1200 1400 1600 1800
07218-110
200
150
100 1 BANK CMOS 2 BANKS LVDS ALL BANKS LVDS 0 25 50 75 100 125 150 175 200 225 250
50
0
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 10. LVDS Current vs. Frequency; All Banks Set to LVDS
500 450 400 350 300 250 200 150 100 50 0 0.5 1.0 1.5 2.0 2.5
07218-011
Figure 13. LVDS/CMOS Current vs. Frequency with Various Logic Combinations
55 54 53 52
DUTY CYCLE (%)
JITTER (fs rms)
51 50 49 48 47 46 45 0 50 100 150 200 250
0
INPUT SLEW RATE (V/ns)
FREQUENCY (MHz)
Figure 11. Additive Broadband Jitter vs. Input Slew Rate
Figure 14. CMOS Output Duty Cycle vs. Frequency (10 pF Load)
Rev. 0 | Page 10 of 16
ADCLK854
1
07218-015
1
07218-018
CH1 300mV
1.25ns/DIV
CH1
954mV
CH1 300mV
5.0ns/DIV
CH1
954mV
Figure 15. CMOS Output Waveform @ 200 MHz (10 pF Load)
1.9 1.8 1.7
OUTPUT SWING (V)
Figure 18. CMOS Output Waveform @ 50 MHz (10 pF Load)
1.8 RLOAD = 750
25C
OUTPUT SWING (V)
RLOAD = 1k
1.7
1.6 85C 1.5 1.4 1.3 1.2 1.1 50
1.6 RLOAD = 500 RLOAD = 300 1.5
07218-016
100
150 FREQUENCY (MHz)
200
250
0
50
100
150
200
250
FREQUENCY (MHz)
Figure 16. CMOS Output Swing vs. Frequency by Temperature (10 pF Load)
2.0 1.9 1.8
OUTPUT SWING (V)
Figure 19. CMOS Output Swing vs. Frequency by Resistive Load
CL = 5pF
1.7 1.6 1.5 1.4 1.3 1.2 1.1 0 50 100
CL = 10pF
CL = 20pF
150
200
250
FREQUENCY (MHz)
Figure 17. CMOS Output Swing vs. Frequency by Capacitive Load
07218-017
1.0
Rev. 0 | Page 11 of 16
07218-019
1.4
ADCLK854 FUNCTIONAL DESCRIPTION
The ADCLK854 accepts a clock input from one of two inputs and distributes the selected clock to all output channels. The outputs are grouped into three banks of four and can be set to either LVDS or CMOS levels. This allows the selection of multiple logic configurations ranging from 12 LVDS to 24 CMOS outputs, along with other combinations using both types of logic. The second option allows the use of the VREF pin to set the dc bias level for the ADCLK854. The VREF pin can be connected to CLKx and CLKx through resistors. This method allows lower impedance termination of signals at the ADCLK854 (for more information, see Figure 32). The internal bias resistors remain in parallel with the external biasing. However, the relatively high impedance of the internal resistors allows the external termination to VREF to dominate. This method is also useful when offsetting the inputs; using only the internal biasing, as previously mentioned, is not desirable.
CLOCK INPUTS
The ADCLK854 differential inputs are internally self-biased. The clock inputs have a resistor divider that sets the commonmode level for the inputs. The complementary inputs are biased about 30 mV lower than the true input to avoid oscillations if the input signal stops. See Figure 20 for the equivalent input circuit. The inputs can be ac-coupled or dc-coupled. Table 8 displays a guide for input logic compatibility. A single-ended input can be accommodated by ac or dc coupling to one side of the differential input; bypass the other input to ground with a capacitor. Note that jitter performance degrades with low input slew rate, as shown in Figure 11. See Figure 27 through Figure 32 for different termination schemes.
VS 9k CLKx 9k 10k 10k 9.5k CLKx 8.5k GND
07218-020
CLOCK OUTPUTS
Each driver consists of a differential LVDS output or two singleended CMOS outputs (always in phase). When the LVDS driver is enabled, the corresponding CMOS driver is in tristate; when the CMOS driver is enabled, the corresponding LVDS driver is powered down and tristated. Figure 21 and Figure 22 display the equivalent output stage.
VS 3.5mA
OUTx OUTx
3.5mA
Figure 20. ADCLK854 Input Stage
Figure 21. LVDS Output Simplified Equivalent Circuit
VS VS
AC-COUPLED INPUT APPLICATIONS
The ADCLK854 offers two options for ac coupling. The first option requires no external components (excluding the dc blocking capacitor), it allows the user to simply couple the reference signal onto the clock input pins. For more information, see Figure 29.
Table 8. Input Logic Compatibility
Supply (V) 3.3 2.5 1.8 3.3 2.5 1.8 1.5 3.3 2.5 1.8 Logic CML CML CML CMOS CMOS CMOS HSTL LVDS LVPECL LVPECL LVPECL Common Mode (V) 2.9 2.1 1.4 1.65 1.25 0.9 0.75 1.25 2.0 1.2 0.5 Output Swing (V) 0.8 0.8 0.8 3.3 2.5 1.8 0.75 0.4 0.8 0.8 0.8 AC-Coupled Yes Yes Yes Not allowed Not allowed Yes Yes Yes Yes Yes Yes DC-Coupled Not allowed Not allowed Yes Not allowed Not allowed Yes Yes Yes Not allowed Yes Yes
OUTA OUTB
07218-022
Figure 22. CMOS Output Equivalent Circuit
Rev. 0 | Page 12 of 16
07218-021
ADCLK854
CONTROL AND FUNCTION PINS
CTRL_A--Logic Select
This pin selects either CMOS (high) or LVDS (low) logic for Output 3, Output 2, Output 1, and Output 0. This pin has an internal 200 k pull-down resistor. with adequate capacitance (>10 F), and bypassing all power pins with adequate capacitance (0.1 F) as close to the part as possible. The layout of the ADCLK854 evaluation board (ADCLK854/PCBZ) provides a good layout example.
Exposed Metal Paddle
The exposed metal paddle on the ADCLK854 package is an electrical connection as well as a thermal enhancement. For the device to function properly, the paddle must be properly attached to ground (GND). The ADCLK854 dissipates heat through its exposed paddle. The PCB acts as a heat sink for the ADCLK854. The PCB attachment must provide a good thermal path to a larger heat dissipation area, such as the ground plane on the PCB. This requires a grid of vias from the top layer down to the ground plane. See Figure 23 for an example.
CTRL_B--Logic Select
This pin selects either CMOS (high) or LVDS (low) logic for Output 7, Output 6, Output 5, and Output 4. This pin has an internal 200 k pull-down resistor.
CTRL_C--Logic Select
This pin selects either CMOS (high) or LVDS (low) logic for Output 11, Output 10, Output 9, and Output 8. This pin has an internal 200 k pull-down resistor.
IN_SEL--Clock Input Select
A logic low selects CLK0 and CLK0 whereas a logic high selects CLK1 and CLK1. This pin has an internal 200 k pull-down resistor.
VIAS TO GND PLANE
Sleep Mode
Sleep mode powers down the chip except for the internal band gap. The input is active high, which puts the outputs into a high-Z state. This pin has a 200 k pull-down resistor.
07218-023
POWER SUPPLY
The ADCLK854 requires a 1.8 V 5% power supply for VS. Best practice recommends bypassing the power supply on the PCB
Figure 23. PCB Land for Attaching Exposed Paddle
Rev. 0 | Page 13 of 16
ADCLK854 APPLICATIONS INFORMATION
USING THE ADCLK854 OUTPUTS FOR ADC CLOCK APPLICATIONS
Any high speed, analog-to-digital converter (ADC) is extremely sensitive to the quality of the sampling clock provided by the user. An ADC can be thought of as a sampling mixer, and any noise, distortion, or timing jitter on the clock is combined with the desired signal at the analog-to-digital output. Clock integrity requirements scale with the analog input frequency and resolution, with higher analog input frequency applications at 14-bit resolution being the most stringent. The theoretical SNR of an ADC is limited by the ADC resolution and the jitter on the sampling clock. Considering an ideal ADC of infinite resolution where the step size and quantization error can be ignored, the available SNR can be expressed approximately by 1 SNR = 20 x log 2f ATJ where fA is the highest analog frequency being digitized and TJ is the rms jitter on the sampling clock. Figure 24 shows the required sampling clock jitter as a function of the analog frequency and effective number of bits (ENOB). For more information, see Application Note AN-756 and Application Note AN-501 at www.analog.com.
110 100 90 80
SNR (dB)
LVDS CLOCK DISTRIBUTION
The ADCLK854 provides clock outputs that are selectable as either CMOS or LVDS level outputs. LVDS is a differential output option that uses a current-mode output stage. The nominal current is 3.5 mA, which yields 350 mV output swing across a 100 resistor. The LVDS output meets or exceeds all ANSI/TIA/EIA-644 specifications. A recommended termination circuit for the LVDS outputs is shown in Figure 25. If ac coupling is necessary, place decoupling capacitors either before or after the 100 termination resistor. See Application Note AN-586 at www.analog.com for more information on LVDS.
VS VS
LVDS
100 100 DIFFERENTIAL (COUPLED)
LVDS
07218-025
Figure 25. LVDS Output Termination
CMOS CLOCK DISTRIBUTION
The output drivers of the ADCLK854 can be configured as CMOS drivers. When selected as a CMOS driver, each output becomes a pair of CMOS outputs. These outputs are 1.8 V CMOS compatible. When single-ended CMOS clocking is used, some of the following guidelines apply. Design point-to-point connections such that each driver has only one receiver, if possible. Connecting outputs in this manner allows for simple termination schemes and minimizes ringing due to possible mismatched impedances on the output trace. Series termination at the source is generally required to provide transmission line matching and/or to reduce current transients at the driver. The value of the resistor (typically 10 to 100 ) is dependent on the board design and timing requirements. CMOS outputs are also limited in terms of the capacitive load or trace length that they can drive. Typically, trace lengths less than 3 inches are recommended to preserve signal rise/fall times and signal integrity.
07218-026
1 SNR = 20log 2f T AJ
18 16
TJ = 100 fS 200 400 f 1ps 2ps
14 12 10 8 6
07218-024
fS
S
70 60 50 40 30 10
10p s
100
1k
fA FULL-SCALE SINE WAVE ANALOG FREQUENCY (MHz)
ENOB
Figure 24. SNR and ENOB vs. Analog Input Frequency
Many high performance ADCs feature differential clock inputs to simplify the task of providing the required low jitter clock on a noisy PCB. Distributing a single-ended clock on a noisy PCB can result in coupled noise on the sample clock. Differential distribution has inherent common-mode rejection that can provide superior clock performance in a noisy environment. Consider the input requirements of the ADC (differential or single-ended, logic level, and termination) when selecting the best clocking/converter solution.
CMOS
10
60.4 1.0 INCH CMOS MICROSTRIP
Figure 26. Series Termination of CMOS Output
Termination at the far end of the PCB trace is a second option. The CMOS outputs of the ADCLK854 do not supply enough current to provide a full voltage swing with a low impedance resistive, far end termination, as shown in Figure 27. The far end termination network should match the PCB trace impedance and provide the desired switching point. The reduced signal swing may
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ADCLK854
still meet receiver input requirements in some applications. This can be useful when driving long trace lengths on less critical networks.
VS 10 50 100 CMOS 100
07218-027
CLK CLK 50 50
VCC - 2V
CMOS
CLK CLK 50 50
07218-030
Figure 27. CMOS Output with Far End Termination
Because of the limitations of single-ended CMOS clocking, consider using differential outputs when driving high speed signals over long traces. The ADCLK854 offers LVDS outputs that are better suited for driving long traces wherein the inherent noise immunity of differential signaling provides superior performance for clocking converters.
VCC - 2V
Figure 30. Typical AC-Coupled or DC-Coupled PECL Configuration (See Table 8 for LVPECL DC-Coupling Limitations)
CLK CLK
CLK CLK
INPUT TERMINATION OPTIONS
For single-ended operation always bypass unused input to GND, as shown in Figure 31. Figure 32 illustrates the use of VREF to provide low impedance termination into VS/2. In addition, a way to negate the 30 mV input offset is with external resistor values; for example, using a 1.8 V CMOS with long traces to provide far end termination.
CLK 100 CLK
CLK CLK
Figure 31. Typical 1.8 V CMOS Configurations for Short Trace Lengths (See Table 8 for CMOS Compatibility)
VREF CLK CLK
07218-032
CLK CLK
07218-028
100
Figure 32. Use of VREF to Provide Low Impedance Termination into VS/2
Figure 28. Typical AC-Coupled or DC-Coupled LVDS or HSTL Configuration (See Table 8 for More Information)
VCC
CLK CLK VCC
CLK CLK
07218-029
Figure 29. Typical AC-Coupled or DC-Coupled CML Configuration (See Table 8 for CML Coupling Limitations)
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07218-031
ADCLK854 OUTLINE DIMENSIONS
7.00 BSC SQ 0.60 MAX 0.60 MAX
37 36
0.30 0.23 0.18
48 1
PIN 1 INDICATOR
PIN 1 INDICATOR 6.75 BSC SQ
0.50 BSC
(BOT TOM VIEW)
EXPOSED PAD
*2.90 2.80 SQ 2.70
25 24
13
12
TOP VIEW 1.00 0.85 0.80 SEATING PLANE 12 MAX 0.80 MAX 0.65 TYP
0.50 0.40 0.30
0.20 MIN
5.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF *COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 WITH EXCEPTION TO EXPOSED PAD DIMENSION.
Figure 33. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 7 mm x 7 mm Body, Very Thin Quad CP-48-6 Dimensions shown in millimeters
ORDERING GUIDE
Model ADCLK854BCPZ 1 ADCLK854BCPZ-REEL71 ADCLK854/PCBZ1
1
Temperature Range -40C to +85C -40C to +85C
Package Description 48-Lead LFCSP_VQ 48-Lead LFCSP_VQ Evaluation Board
Package Option CP-48-6 CP-48-6
Z = RoHS Compliant Part.
(c)2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07218-0-4/09(0)
Rev. 0 | Page 16 of 16
080508-A

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